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CLOCK.PDS
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1995-02-18
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81 lines
; This example demonstrates the different
; types of clocking you can use in the
; EPX780.
;
; SET COMPILER OPTIONS TO:
; Use Design Pin Assignments, but not
; Previous, Abort on no fit
CHIP product NFX780_84
PIN 3 CLK1 ; synchronous clock pin 1
PIN 45 CLK2 ; synchronous clock pin 2
PIN a[1:2] ; 2 input pins
PIN 5 o1 ; output in CFB #0
; the next two outputs in CFB #0
; use a delayed synchronous clock
PIN 6 o2 DELAYCLK
PIN 7 o3 DELAYCLK
; but the following declaration will
; cause an error. see the note below.
; PIN 7 o3
PIN 81 o4 ; an output in CFB #1
PIN [75:77] o[5:7] ; 3 outputs in CFB #1
EQUATIONS
; o1 will store the logical AND of a1
; and a2 on the falling edge of the
; synchronous clock CLK1
o1 := a1 * a2
o1.CLKF = /CLK1
; o2 will store the logical AND of a1
; and a2 on the rising edge of the
; delayed synchronous clock CLK2
o2 := a1 * a2
o2.CLKF = CLK2
; o3 will store the logical AND of a1
; and a2 on the falling edge of the
; delayed synchronous clock CLK2.
; Once one macrocell in a CFB uses a delayed
; global clock, all the other macrocells
; that use the same clock must also use the
; delayed version whether they want it
; or not. That's because the delay is
; inserted as the clock enters the CFB,
; not on a macrocell-by-macrocell basis.
o3 := a1 * a2
o3.CLKF = /CLK2
; o4 will store the logical AND of a1
; and a2 on the rising edge of the
; synchronous clock CLK2. Note that
; o4 can use CLK2 does not have to use
; the delayed synchronous version of
; CLK2 since it is in a different
; macrocell from o3.
o4 := a1 * a2
o4.CLKF = CLK2
; o5, o6, and o7 all store the logical
; AND of a1 and a2. o5 and o6 use
; asynchronous clocking.
o[5:7] := a1 * a2
o5.ACLK = a1 * a2
o6.ACLK = /a1 * a2
; You can't use more than three different
; asynchronous clocks in a CFB, so the
; following won't work!
; o7.ACLK = /a1 * /a2 ; this won't fit!
; but this is OK since it matches one of
; the previous asynchronous clock expressions
o7.ACLK = a1 * a2 ; this will fit!